The present invention relates in general to data processing systems, and in particular, to the interface between clocked integrated circuit chips in a data processing system.
Data processing systems conventionally include a number of integrated circuit chips. For example, each of the following system elements may be on separate chips: a processor, a memory cache, a memory controller and system memory. Communication paths among the chips may differ in electrical length from one another. Also, any one of the paths may vary somewhat from one manufactured instance to the next, such as due to variation within a manufacturing tolerance, or changes in manufacturing process from one instance to the next. These issues arise not only with respect to signal propagation latency for paths among the chips in the system, but also with respect to latency on the chips themselves.
Such differing latencies among and on chips in a system present problems in synchronizing communication among the chips. For sufficiently large and varying latencies, it is conventional to communicate among chips over a bus using a protocol that includes tagging requests and responses. However this may slow communication, and adds substantial complexity. Where latency is small enough and its variation is sufficiently constrained, it is desirable to synchronize communication among chips merely by reference to clock signals on or among the chips. That is, it is desirable to synchronize communication without resorting to bus protocols that may include tagging of transactions.